The present invention relates to an insulated gate type semiconductor device in which a plurality of cells, each having a MOS structure, are provided on a principal plane of the same semiconductor substrate or layer and a connecting conductor is fixedly attached to a part of a common electrode which is connected to respective semiconductor cells.
Demand for a power switching element with higher withstand voltage, higher power, and a higher speed has increased in recent years. Accordingly, the use of a vertical type power MOSFET (insulated gate MOSFET), which controls an electric current which is in contact with both principal planes of a semiconductor substrate by means of a plurality of MOS structures provided on the surface has grown rapidly, with use as a switching power supply being the principal application. Furthermore, the range of principal use of a conductivity modulation type MOSFET, in which a layer of a different conductive type, or conductivity type, which terms shall be used interchangeably, is provided on the opposite side of the principal plane on which the MOS structure is installed and in which ON resistance is lowered by utilizing conductivity modulation, is increasing through the use of inverter controls for which higher withstand voltage and higher power are required. The conductivity modulation type MOSFET is also referred to as an insulated gate type bipolar transistor, and abbreviated as IGBT hereinafter.
FIG. 2 shows a structure of an IGBT, in which an n.sup.- type drift region or first semiconductor layer 2, of high resistance is laminated on a p.sup.+ type substrate or second semiconductor layer 1 which becomes a collector region. In the surface layer of the drift region 2, a plurality of p-type channel diffused regions (base regions) 3 are formed, and p.sup.+ wells 4, of low resistance, are provided at the centers thereof. A pair of limited regions which are either emitter regions, in the case of a bipolar device, or source regions in the case of a field effect device, and which are, in this case n.sup.+ type emitter regions 5 are formed at a space in the surface layer of the base regions 3. In a hybrid insulated gate type device the limited regions 5 may be emitter regions in the base of one device and source regions in the base of an adjacent device. In order to form an n-type channel in a surface layer 31 of the channel diffused regions 3 which is between the drift region 2 and the emitter regions 5, a gate electrode 7 which is connected to a gate terminal G is provided through a gate oxide film 6. A common emitter electrode 9 which is in contact with p.sup.+ wells 4, and also in contact with the emitter regions 5 of individual cells, is provided. A conductor 11, for connecting the emitter electrode 9 to an emitter terminal E, is provided, for instance by bonding an aluminum wire to the emitter electrode. Furthermore, a collector electrode 10, connected to a collector terminal C, is in contact with the collector region 1.
FIG. 3 shows the structure of a power MOSFET, in which an n.sup.- type drain region 22, of high resistance, is laminated on an n.sup.+ type substrate 21 which becomes a drain contact layer. A plurality of p-type channel diffused regions (base regions) 3 are formed in the surface layer of the drain region 22, and p.sup.+ wells 4 with low resistance are provided at the centers thereof. A pair of limited regions, in this case n.sup.+ type source regions 25 are formed at a portion or a space in the surface layer of the channel diffused region or base region 3. In order to form an n-type channel in a surface layer 31 of the base region 3 which is put between the drain region 22 and the source region 25, a gate electrode 7 which is connected to a gate terminal G is provided through a gate oxide film 6. A common source electrode 29 which is in contact with the p.sup.+ well 4, and also in contact with the source region 25 of individual cells, is provided. A conductor 11, for connecting the source electrode 29, to a source terminal S, is fixedly attached, for instance by bonding an Al wire to the source terminal. Furthermore, a drain electrode 30, connected to a drain terminal D, is in contact with the drain contact layer 21.
In the IGBT shown in FIG. 2, the emitter region 5, the base region 3 and the drift region 2 form an npn transistor 41 which is a first parasitic bipolar transistor. The base region 3, the drift region 2 and the collector region 1 form a pnp transistor 42, which is a second parasitic bipolar transistor. These transistors have current gains .alpha.1 and .alpha.2, respectively, and show a pnpn thyristor structure, which latches under the ON state when the sum of the current gains is greater than or equal to 1, that is when .alpha.1+.alpha.2.gtoreq.1. When the parasitic thyristor latches, the IGBT loses gate control of the electric current and is led to breakdown finally. This phenomenon is called latch-up.
In the power MOSFET shown in FIG. 3, the source region 25, the base region 3 and the drain region 22 form a parasitic npn bipolar transistor 41. One of the causes of activation of this parasitic bipolar transistor is the flow of the majority carrier in the base region which flows to the source electrode 29 through the base region 3 just under the source region 25. This flow of carrier generates voltage drop along the source and base junction portion. When this voltage drop exceeds the threshold voltage of approximately 0.7 V, this junction portion is biased in the forward direction and this parasitic bipolar transistor is turned ON. When this happens, control of the electric current in the MOSFET with the gate signal becomes impossible thus leading to breakdown. This phenomenon is called latch-back.
As described, both the IGBT and the insulated gate type MOSFET include either a parasitic pnpn thyristor or a parasitic npn transistor as shown in FIG. 2 and FIG. 3, respectively. These parasitic elements lead to sudden latch-up or latch-back phenomenon, particularly at high voltage, high electric current and high temperature. The control function of the gate is lost, thus leading to breakdown. In a conventional IGBT and insulated gate type MOSFET, measures such as reduction of the base resistance by means of the p.sup.+ well 4, reduction of majority carrier in the base region (See L. A. Goodman: International Electron Devices Meeting, 1984), or reduction of the electric current, which is concentrated in the vicinity of the emitter and base junction portion of a cell (See Yilmaz U.S. Pat. No. 4,809,045) have been taken for the purpose of preventing activation of these parasitic elements. However, satisfactory results have not been obtained with these measures.
Accordingly, it is an object of the present invention to solve the above-described problems and to provide an insulated gate type semiconductor device having an enlarged application range by preventing latch-up and latch-back phenomena caused by parasitic element activation.